QSC Post Quantum Cryptographic Library 1.0.0.6c (A6)
A post quantum secure library written in Ansi C
 
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qsc_cpuidex_cpu_features Struct Reference

Contains the CPU feature availability. More...

#include <cpuidex.h>

Data Fields

bool adx
 
bool aesni
 
bool pcmul
 
bool armv7
 
bool neon
 
bool sha256
 
bool sha512
 
bool sha3
 
bool avx
 
bool avx2
 
bool avx512f
 
bool hyperthread
 
bool rdrand
 
bool rdtcsp
 
uint32_t cacheline
 
uint32_t cores
 
uint32_t cpus
 
uint32_t freqbase
 
uint32_t freqmax
 
uint32_t freqref
 
uint32_t l1cache
 
uint32_t l1cacheline
 
uint32_t l2associative
 
uint32_t l2cache
 
char serial [QSC_CPUIDEX_SERIAL_SIZE]
 
char vendor [QSC_CPUIDEX_VENDOR_SIZE]
 
qsc_cpuidex_cpu_type cputype
 

Detailed Description

Contains the CPU feature availability.

This structure holds flags and parameters indicating the availability of various CPU features such as AES-NI, AVX, NEON, and others. It also stores details about cache sizes, frequency, and manufacturer-specific information.

Field Documentation

◆ adx

bool adx

[bool] True if ADX instructions are available.

◆ aesni

bool aesni

[bool] True if AES-NI instructions are available.

◆ armv7

bool armv7

[bool] True if ARMv7 features are detected.

◆ avx

bool avx

[bool] True if AVX instructions are available.

◆ avx2

bool avx2

[bool] True if AVX2 instructions are available.

◆ avx512f

bool avx512f

[bool] True if AVX512 Foundation instructions are available.

◆ cacheline

uint32_t cacheline

[uint32_t] The CPU cache line size (in bytes).

◆ cores

uint32_t cores

[uint32_t] The number of physical cores.

◆ cpus

uint32_t cpus

[uint32_t] The number of logical processors (CPUs).

◆ cputype

[qsc_cpuidex_cpu_type] CPU manufacturer type.

◆ freqbase

uint32_t freqbase

[uint32_t] The base CPU frequency (in Hz).

◆ freqmax

uint32_t freqmax

[uint32_t] The maximum CPU frequency (in Hz).

◆ freqref

uint32_t freqref

[uint32_t] The reference CPU frequency (in Hz).

◆ hyperthread

bool hyperthread

[bool] True if hyper-threading is enabled.

◆ l1cache

uint32_t l1cache

[uint32_t] The size of the L1 cache (in bytes).

◆ l1cacheline

uint32_t l1cacheline

[uint32_t] The L1 cache line size (in bytes).

◆ l2associative

uint32_t l2associative

[uint32_t] The associativity of the L2 cache.

◆ l2cache

uint32_t l2cache

[uint32_t] The size of the L2 cache (in bytes).

◆ neon

bool neon

[bool] True if NEON SIMD instructions are available.

◆ pcmul

bool pcmul

[bool] True if PCLMULQDQ (carry-less multiplication) is available.

◆ rdrand

bool rdrand

[bool] True if the RDRAND instruction is supported.

◆ rdtcsp

bool rdtcsp

[bool] True if the RDTCSP instruction is supported.

◆ serial

[char[]] CPU serial number.

◆ sha256

bool sha256

[bool] True if SHA-256 instructions are available.

◆ sha3

bool sha3

[bool] True if SHA3 instructions are available.

◆ sha512

bool sha512

[bool] True if SHA-512 instructions are available.

◆ vendor

[char[]] CPU vendor name.


The documentation for this struct was generated from the following file: